The present invention relates to an electric field intensity detecting circuit and a limiter amplifier and particularly concerns an electric field intensity detecting circuit improved to obtain an electric field intensity detecting signal with preferred linearity and a limiter amplified used for the circuit.
In general, electric field intensity detecting circuits are used for electronic equipment such as a radio receiver, a portable phone, a cordless phone, and a television receiving set that receives and processes a high-frequency signal (RF signal). The electric field intensity detecting circuits detect electric field intensity of a received high-frequency signal and output a DC signal at a level equivalent to the electric field intensity.
FIG. 1 is a diagram showing the configuration of a conventional electric field intensity detecting circuit. In FIG. 1, a high-pass filter 1 on the input stage is constituted by a capacitor C and a resistor R. n differential amplifiers 2, 3, and 4 make multi-stage connection to the post stage of the high-pass filter 1. The n differential amplifiers 2, 3, and 4 making multi-stage connection constitute a limiter amplifier.
The differential amplifiers 2, 3, and 4 are each constituted by a differential pair of two resistors Ri1 and Ri2 (i=1 to n) and two transistors Qi1 and Qi2 (i=1 to n) and a constant current circuit Ii (i=1 to n). Namely, the sources of the two transistors Qj1 and Qi2 constituting each differential pair are connected in common, and the constant current circuits Ii (i=1 to n) are respectively connected to the common sources. Further, the common sources of the transistors Qi1 and Qi2 are each connected to a constant current circuit I via transistors Qi (i=1 to n).
Moreover, the drains of the transistors Qi1 and Qi2 are connected to a power supply VDD respectively via the resistors Ri1 and Ri2. Also, except for the differential amplifier 2 on the first stage, an output signal VOUTi (i=1 to nxe2x88x921) from the differential amplifier on the preceding stage is inputted to the gates of the transistors Qi1 and Qi2. An input signal Vin passing through the high-pass filter 1 is inputted to the gates of the transistors Q11 and Q12 of the differential amplifier 2 on the first stage.
The above-described transistors Qi and the constant current circuits I form a part of a detector circuit connected to the post stage of the limiter amplifier. The detector circuit inputs output signals of the n differential amplifiers 2, 3, and 4, smooth the signals, and outputs the signals, so that a DC electric field intensity detecting signal VDC is obtained.
FIG. 2 is a diagram showing input/output characteristics of the electric field intensity detecting circuit, that is, the relationship between the input signal Vin (voltage value) and the output signal VDC (voltage value). In the electric field intensity detecting circuit, it is desirable to have preferable linearity as much as possible between a logarithm of an input voltage Vin and an output voltage VDC. For example, in the case of a radio receiver, it is necessary to have linearity over a wide range of about [dBxcexc] (1 xcexcV) to 80 [dBxcexc] (10 mV). For this reason, a plurality of differential amplifiers constituting a limiter amplifier are provided and are connected in multistages, and the differential amplifiers 2, 3, and 4 on the respective stages are adjusted in gain according to a magnitude of current applied to the constant current circuits Ii (i=1 to n).
Namely, in the limiter amplifier configured thus, the signal Vin inputted to the transistors Q11 and Q12 of the differential amplifier 2 on the first stage is amplified by a predetermined level and is outputted. In this circuit, the transistor Q11 has an opposite phase output and the transistor Q12 has an in-phase output. The amplified and outputted signal is inputted to the bases of the transistors Q21 and Q22 of the differential amplifier 3 on the second stage, and the signal is further amplified by the differential amplifier 3 and is outputted.
Thereafter, the signal is similarly amplified increasingly by the differential amplifiers 2, 3, and 4 on the respective stages. Hence, the signal Vin inputted to the differential amplifier 2 on the first stage increases in amplitude as the signal proceeds to latter stages. However, since signal output levels on the respective stages do not exceed the power supply voltage VDD, saturation is made without amplification exceeding a certain level of the signal inputted to each of the stages.
Since a signal inputted to the differential amplifier 4 on the nth stage has the highest level as compared with the other stages, saturation is made most quickly at a low input level. Meanwhile, since a signal input level Vin on the first stage is the lowest as compared with the other stages, saturation cannot be made without inputting up to a high-input level. By smoothing output voltages of the differential amplifiers 2, 3, and 4 on the respective stages that have such characteristics, preferable linearity is obtained as much as possible as shown in FIG. 2.
In the case where a differential amplifier constituting a limiter amplifier is provided only on a single stage, when an amplification factor is large, a signal level is immediately saturated, and when an amplification factor is small, it takes a long time to perform amplification to a desired level. Thus, preferable linearity cannot be obtained with respect to the input/output characteristics. Hence, as described above, a plurality of amplifiers 2, 3, and 4 are connected in multistages to constitute the limiter amplifier.
In this case, in order to obtain a predetermined gain in each of the differential amplifiers 2, 3, and 4 on the respective stages, current needs to be applied to the constant current circuits Ii (i=1 to n) on the respective stages so as to match the gain. At this point, since the differential amplifier 4 on the nth stage has the largest gain, the corresponding constant current circuit In has to be fed with larger current as compared with the other stages.
However, when current applied to the constant current circuits Ii (i=1 to n) is increased to obtain a large gain, the levels of signals (voltage levels of nodes al to an shown in FIG. 1) inputted to the transistors Qi (i=1 to n) constituting the detector circuit become lower than the original level, resulting in degradation in DC detection efficiency. This will be described below in accordance with FIG. 3.
FIG. 3 is a diagram showing waveforms of signals (signals indicated on the nodes al to an) inputted to the gates of the transistors Qi (i=1 to n). Since the constant current circuit Ii increases in current value with latter stages (the node an side) of the limiter amplifier, as shown in FIG. 3, a signal level on the post-stage side peaks out and becomes lower than the original level. Hence, DC detection efficiency is reduced and a signal remaining AC passes particularly on the post-stage side. Thus, the above-described linearity cannot be obtained.
The present invention is devised to solve such a problem and has as its object the provision of preferable DC detection efficiency while obtaining a large gain of a limiter amplifier having differential amplifiers connected in multistages.
An electric field intensity detecting circuit comprises a differential amplifier circuit constituted by first differential amplifiers connected in multistages, the first differential amplifiers amplifying an input signal from the preceding stage and outputting the signal to the subsequent stage, and second differential amplifiers arranged only in parallel with some of the n first differential amplifiers on a post-stage side, the n first differential amplifiers constituting the differential amplifier circuit, and a to-be-detected signal is obtained from the second differential amplifiers.
Further, a limiter amplifier of the present invention comprises a differential amplifier circuit constituted by first differential amplifiers connected in multistages, the first differential amplifiers amplifying an input signal from the preceding stage and outputting the signal to the subsequent stage, and second differential amplifiers arranged only in parallel with some of the n first differential amplifiers on the post-stage side, the n first differential amplifiers constituting the differential amplifier circuit.
Since the present invention is achieved by the above technical means, differential amplification is increased in gain by applying large current to the first constant current circuit constituting the first differential amplifier, and the signal level for detection can be increased by applying small current to the second constant current circuit constituting the second differential amplifier. Hence, preferable detection efficiency can be obtained while a large gain is provided for differential amplification.
Further, the second differential amplifiers are arranged only in parallel with some of the n first differential amplifiers, for instance some of the first differential amplifiers on a post-stage side that require particularly a large gain for differential amplification. Thus, it is possible to minimize an increase in the number of elements. With this configuration, while suppressing expansion of a circuit area increased with the number of elements, preferable detection efficiency can be obtained with a large gain for differential amplification.